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ML4824
Power Factor Correction and PWM Controller Combo
Features
* Internally synchronized PFC and PWM in one IC * Low total harmonic distortion * Reduces ripple current in the storage capacitor between the PFC and PWM sections * Average current, continuous boost leading edge PFC * Fast transconductance error amp for voltage loop * High efficiency trailing edge PWM can be configured for current mode or voltage mode operation * Average line voltage compensation with brownout control * PFC overvoltage comparator eliminates output "runaway" due to load removal * Current fed gain modulator for improved noise immunity * Overvoltage protection, UVLO, and soft start
General Description
The ML4824 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-2-3 specification. The ML4824 includes circuits for the implementation of a leading edge, average current, "boost" type power factor correction and a trailing edge, pulse width modulator (PWM). The device is available in two versions; the ML4824-1 (fPWM = fPFC) and the ML4824-2 (fPWM = 2 x fPFC). Doubling the switching frequency of the PWM allows the user to design with smaller output components while maintaining the best operating frequency for the PFC. An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brown-out protection. The PWM section can be operated in current or voltage mode at up to 250kHz and includes a duty cycle limit to prevent transformer saturation.
Block Diagram
16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7 RAMP 2 8 8V VDC 6 VCC SS 5 8V DC ILIMIT 9 PULSE WIDTH MODULATOR VCCZ UVLO 50A 1.25V
- + - +
1 IEAO POWER FACTOR CORRECTOR OVP +
+ - -
13 VCC VCCZ 13.5V 7.5V REFERENCE S -1V
+ -
VEA -
+
VREF 14
3.5k
IEA +
2.7V
-
Q
GAIN MODULATOR 3.5k
R S
Q PFC OUT Q 12
PFC ILIMIT
R OSCILLATOR (-2 VERSION ONLY) x2 DUTY CYCLE LIMIT
Q
PWM OUT S VFB 2.5V
- +
Q
VIN OK 1V
- +
11
R DC ILIMIT
Q
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ML4824
PRODUCT SPECIFICATION
Pin Configuration
ML4824 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W)
IEAO IAC ISENSE VRMS SS VDC RAMP 1 RAMP 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VEAO VFB VREF VCC PFC OUT PWM OUT GND DC ILIMIT
TOP VIEW
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME IEAO IAC ISENSE VRMS SS VDC RAMP 1 RAMP 2 DC ILIMIT GND PWM OUT PFC OUT VCC VREF VFB VEAO PFC gain control reference input Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft start capacitor PWM voltage feedback input Oscillator timing node; timing set by RTCT When in current mode, this pin functions as as the current sense input; when in voltage mode, it is the PWM input from PFC output (feed forward ramp). PWM current limit comparator input Ground PWM driver output PFC driver output Positive supply (connected to an internal shunt regulator) Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output FUNCTION PFC transconductance current error amplifier output
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PRODUCT SPECIFICATION
ML4824
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter VCC Shunt Regulator Current ISENSE Voltage Voltage on Any Other Pin IREF IAC Input Current Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink PFC OUT, PWM OUT Energy Per Cycle Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (JA) Plastic DIP Plastic SOIC -65 -3 GND - 0.3 Min. Max. 55 5 VCCZ + 0.3 20 10 500 500 1.5 150 150 260 80 105 Units mA V V mA mA mA mA J C C C C/W C/W
Operating Conditions
Temperature Range
Parameter ML4824CX ML4824IX Min. 0 -40 Max. 70 85 Units C C
Electrical Characteristics
Unless otherwise specified, ICC = 25mA, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio Current Error Amplifier Input Voltage Range Transconductance Input Offset Voltage
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Conditions
Min. 0
Typ. Max. Units 7 85 2.53 -0.3 6.7 0.6 1.0 -80 80 75 75 2 195 8 310 15 120 2.60 -1.0 V V A V V A A dB dB V mV 3
Voltage Error Amplifier VNON INV = VINV, VEAO = 3.75V Note 2 6.0 VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V VCCZ - 3V < VCC < VCCZ - 0.5V -40 40 60 60 -1.5 VNON INV = VINV, VEAO = 3.75V 130 0 50 2.46
ML4824
PRODUCT SPECIFICATION
Electrical Characteristics (continued) Unless otherwise specified, ICC = 25mA, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1)
Symbol Parameter Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio OVP Comparator Threshold Voltage Hysteresis PFC ILIMIT Comparator Threshold Voltage (PFC ILIMIT VTH - Gain Modulator Output) Delay to Output DC ILIMIT Comparator Threshold Voltage Input Bias Current Delay to Output VIN OK Comparator Threshold Voltage Hysteresis Gain Modulator Gain (Note 3) IAC = 100A, VRMS = VFB = 0V IAC = 50A, VRMS = 1.2V, VFB = 0V IAC = 50A, VRMS = 1.8V, VFB = 0V IAC = 100A, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage Oscillator Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage Dead Time CT Discharge Current Reference Output Voltage TA = 25C, I(VREF) = 1mA 7.4 7.5 7.6 V PFC Only VRAMP 2 = 0V, VRAMP 1 = 2.5V 270 4.5 Line, Temp 68 2.5 370 7.5 470 9.5 TA = 25C VCCZ - 3V < VCC < VCCZ - 0.5V 71 76 1 2 84 81 kHz % % kHz V ns mA IAC = 100A IAC = 250A, VRMS = 1.15V, VFB = 0V 0.74 0.36 1.20 0.55 0.14 0.55 1.80 0.80 0.20 10 0.82 0.90 0.66 2.24 1.01 0.26 MHz V 2.4 0.8 2.5 1.0 2.6 1.2 V V 0.97 1.02 0.3 150 1.07 1 300 V A ns -0.8 100 -1.0 -1.15 190 150 300 V mV ns 2.6 80 2.7 115 2.8 150 V mV VCCZ - 3V < VCC < VCCZ - 0.5V VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V -40 40 60 60 6.0 Conditions Min. Typ. Max. Units -0.5 6.7 0.6 -90 90 75 75 1.0 -1.0 A V V A A dB dB
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PRODUCT SPECIFICATION
ML4824
Electrical Characteristics (continued) Unless otherwise specified, ICC = 25mA, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1)
Symbol Parameter Line Regulation Load Regulation Temperature Stability Total Variation Long Term Stability PFC Minimum Duty Cycle Maximum Duty Cycle Output Low Voltage VIEAO > 4.0V VIEAO < 1.2V IOUT = -20mA IOUT = -100mA IOUT = 10mA, VCC = 8V Output High Voltage Rise/Fall Time PWM Duty Cycle Range Output Low Voltage ML4824-1 ML4824-2 IOUT = -20mA IOUT = -100mA IOUT = 10mA, VCC = 8V Output High Voltage Rise/Fall Time Supply Shunt Regulator Voltage (VCCZ) VCCZ Load Regulation VCCZ Total Variation Start-up Current Operating Current Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis
Notes 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. Includes all bias currents to other circuits connected to the VFB pin. 3. Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5V)-1.
Conditions VCCZ - 3V < VCC < VCCZ - 0.5V 1mA < I(VREF) < 20mA Line, Load, Temp TJ = 125C, 1000 Hours
Min.
Typ. Max. Units 2 2 0.4 10 15 7.65 5 25 0 mV mV % V mV % % 0.8 2.0 1.5 V V V V V ns 0-50 0-45 0.8 2.0 1.5 % % V V V V V ns 14.2 14.6 0.7 16 1.0 19 14 3.3 V mV V mA mA V V
7.35
90
95 0.4 0.8 0.7
IOUT = 20mA IOUT = 100mA CL = 1000pF
10 9.5
10.5 10 50
0-44 0-37
0-47 0-40 0.4 0.8 0.7
IOUT = 20mA IOUT = 100mA CL = 1000pF
10 9.5
10.5 10 50
12.8 25mA < ICC < 55mA Load, Temp VCC = 11.8V, CL = 0 VCC < VCCZ - 0.5V, CL = 0 12 2.7 12.4
13.5
100 300
13 3.0
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ML4824
PRODUCT SPECIFICATION
Typical Performance Characteristics
250 250
TRANSCONDUCTANCE ( )
150
TRANSCONDUCTANCE ( )
200
200
Voltage Error Amplifier (VEA) Transconductance (gm)
400 VARIABLE GAIN BLOCK CONSTANT - K
15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7
150
100
100
50
50
0 0 1 2 VFB (V) 3 4 5
0 -500
0 IEA INPUT VOLTAGE (mV)
500
Current Error Amplifier (IEA) Transconductance (gm)
300
200
100
0 0 1 2 3 4 5 VRMS (mV)
Gain Modulator Transfer Characteristic (K)
16 VEAO VFB VEA -
+ -
1 IEAO OVP +
+ -
3.5k
IEA +
2.7V
-
S -1V
+ -
Q
GAIN MODULATOR 3.5k
R S
Q PFC OUT Q 12
PFC ILIMIT
R OSCILLATOR
Q
Figure 1. PFC Section Block Diagram.
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PRODUCT SPECIFICATION
ML4824
Functional Description
The ML4824 consists of an average current controlled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM's line regulation. In either mode, the PWM stage uses conventional trailing-edge duty cycle modulation, while the PFC uses leading-edge modulation. This patented leading/trailing edge modulation technique results in a higher useable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4824-1 runs at the same frequency as the PFC. The PWM section of the ML4824-2 runs at twice the frequency of the PFC, which allows the use of smaller PWM output magnetics and filter capacitors while holding down the losses in the PFC stage power components. In addition to power factor correction, a number of protection features have been built into the ML4824. These include soft-start, PFC over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and undervoltage lockout.
and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current which the converter draws from the power line agrees with the instantaneous line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. The first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. In order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level) from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4824 PFC is of the current-averaging type, no slope compensation is required.
Power Factor Correction
Power factor correction makes a non-linear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of non-linear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect which occurs on the input filter capacitor in these supplies causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other non-linear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the ML4824 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input
PFC Section
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the ML4824. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1. A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. A voltage proportional to the long-term rms AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator's output is inversely proportional to VRMS2 (except at unusually low values of VRMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K, and is illustrated in the Typical Performance Characteristics.
2.
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ML4824
PRODUCT SPECIFICATION
3.
The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage.
VREF
The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is:
I AC x VEAO I GAINMOD ------------------------------- x 1V 2 V RMS (1)
PFC OUTPUT VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 VEA -
+
16 IEAO
1
IEA +
+ - -
GAIN MODULATOR
More exactly, the output current of the gain modulator is given by:
I GAINMOD K x ( VEAO - 1.5V ) x I AC
Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers Overvoltage Protection
where K is in units of V-1. Note that the output current of the gain modulator is limited to 200A.
Current Error Amplifier
The current error amplifier's output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin (current into ISENSE VSENSE/3.5k). The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin.
Cycle-By-Cycle Current Limiter The ISENSE pin, as well as being a part of the current
The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.7V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 125mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.58V. The VFB should be set at a level where the active and passive external power components and the ML4824 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop.
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. There are two major concerns when compensating the voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier's open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the
feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle.
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PRODUCT SPECIFICATION
ML4824
ML4824's voltage error amplifier has a specially shaped nonlinearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Typical Performance Characteristics. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Typical Performance Characteristics. For more information on compensating the current and voltage control loops, see Application Notes 33 and 34. Application Note 16 also contains valuable information for the design of this class of PFC.
Oscillator (RAMP 1)
EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at:
1 f OSC = 100kHz = --------------t RAMP t RAMP = C T x R T x 0.51 = 1 x 10
-5
Solving for RT x CT yields 2 x 10-4. Selecting standard components values, CT = 470pF, and RT = 41.2k. The deadtime of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator deadtime, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. This can be accomplished by using a stable 470pF capacitor for CT.
PWM SECTION
Pulse Width Modulator
The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock:
1 f OSC = -------------------------------------------------t RAMP + t DEADTIME (2)
The deadtime of the oscillator is derived from the following equation:
V REF - 1.25 t RAMP = C T x R T x In ------------------------------- V REF - 3.75 (3)
The PWM section of the ML4824 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing (at the PFC frequency in the ML4824-1, and at twice the PFC frequency in the ML4824-2). The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP 2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter's output stage. DC ILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP 2 in such applications. For voltage-mode operation or certain specialized applications, RAMP 2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input is used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage of the ML4824, as this function is generally performed on the output side of the PWM's isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM's RAMP 2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.25V.
PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle
at VREF = 7.5V:
t RAMP = C T x R T x 0.51
The deadtime of the oscillator may be determined using:
t DEADTIME 2.5V = ----------------- x C T = 490 x C T 5.1mA (4)
The deadtime is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by:
1 f OSC = --------------t RAMP REV. 1.0.4 6/6/01 (5)
current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle.
9
ML4824
PRODUCT SPECIFICATION
VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than
its nominal 2.5V. Once this voltage reaches 2.5V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins.
PWM Control (RAMP 2)
limit the current through the part to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor's value must be chosen to meet the operating current requirement of the ML4824 itself (19mA max) plus the current required by the two gate driver outputs. EXAMPLE: With a VBIAS of 20V, a VCC limit of 14.6V (max) and the ML4824 driving a total gate charge of 110nC at 100kHz (e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate driver current required is:
I GATEDRIVE = 100kHz x 100nC = 11mA 20V - 14.6V R BIAS = -------------------------------------- = 180 19mA + 11mA (7)
When the PWM section is used in current mode, RAMP 2 is generally used as the sampling point for a voltage representing the current in the primary of the PWM's output transformer, derived either by a current sensing resistor or a current transformer. In voltage mode, it is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2), which will have a minimum value of zero volts and should have a peak value of approximately 5V. In voltage mode operation, feedforward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage.
Soft Start
(8)
To check the maximum dissipation in the ML4824, find the current at the minimum VCC (12.4V)::
20V - 12.4V I CC = -------------------------------- = 42.2mA 180 (9)
Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 50A supplies the charging current for the capacitor, and start-up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation::
50A C SS = t DELAY x --------------1.25V (6)
The maximum allowable ICC is 55mA, so this is an acceptable design. The ML4824 should be locally bypassed with a 10nF and a 1F ceramic capacitor. In most applications, an electrolytic capacitor of between 100F and 330F is also required across the part, both for filtering and as part of the start-up bootstrap circuitry.
VBIAS
where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of CSS:
50A C SS = 5ms x --------------- = 200nF 1.25V
RBIAS
VCC ML4824 GND 10nF CERAMIC 1F CERAMIC
Caution should be exercised when using this minimum soft start capacitance value because premature charging of the SS capacitor and activation of the PWM section can result if VFB is in the hysteresis band of the VIN OK comparator at start-up. The magnitude of VFB at start-up is related both to line voltage and nominal PFC output voltage. Typically, a 1.0F soft start capacitor will allow time for VFB and PFC out to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms.
GENERATING VCC
Figure 3. External Component Connections to VCC
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 4 shows a typical trailing edge control scheme.
The ML4824 is a current-fed part. It has an internal shunt voltage regulator, which is designed to regulate the voltage internal to the part at 13.5V. This allows a low power dissipation while at the same time delivering 10V of gate drive at the PWM OUT and PFC OUT outputs. It is important to
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PRODUCT SPECIFICATION
ML4824
In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 5 shows a leading edge control scheme.
One of the advantages of this control teccnique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary "no-load" period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC's output ripple voltage can be reduced by as much as 30% using this method.
L1 + DC I1 VIN
SW2
I2
I3 I4
SW1 C1
RL
RAMP
VEAO REF U3 + EA - DFF RAMP OSC U4 CLK + - U1 R Q D U2 Q CLK VSW1 TIME
TIME
Figure 4. Typical Trailing Edge Control Scheme.
L1 + DC I1 VIN
SW2
I2
I3 I4
SW1 C1
RL
RAMP
VEAO U3 + EA -
REF
VEAO + - CMP U1 DFF R Q D U2 Q CLK VSW1
TIME
RAMP OSC U4 CLK
TIME
Figure 5. Typical Leading Edge Control Scheme.
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ML4824
PRODUCT SPECIFICATION
TYPICAL APPLICATIONS
Figure 6 is the application circuit for a complete 100W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 33.
AC INPUT 85 TO 265VAC
C1 470nF
F1 3.15A L1 3.1mH Q1 IRF840 R2A 357k D1 8A, 600V Q2 R17 IRF830 33 C25 100nF T1 R27 39k R2B 357k R30 4.7k R21 22 R15 3 D6 600V R28 180 C20 1F R24 1.2k D3 50V R7A 178k C7 220pF R12 27k C6 1nF R7B 178k R19 220 R20 1.1 MOC 8102 TL431 R14 33 Q3 IRF830 R23 1.5k C22 4.7F R18 220 R22 8.66k D7 15V T2 D5 600V L2 D11 MBR2545CT 33H C24 1F 12VDC
C4 10nF
C5 100F
BR1 4A, 600V R1A 499k
C21 1800F
RTN
C3 470nF
R1B 499k R3 75k
C30 330F
C12 10F
D12 1A, 50V D13 1A, 50V
R26 10k
C23 100nF R25 2.26k
C2 470nF
R4 13k
1 2 3
R5 300m 1W
IEAO IAC ISENSE VRMS SS VDC RAMP 1 RAMP 2
VEAO VFB VREF VCC PFC OUT PWM OUT GND DC ILIMIT
16 15 14 13 12 11 10 9
D8 1A, 20V C15 10nF C16 1F C13 100nF C14 1F R8 2.37k C31 1nF R11 750k C8 82nF C9 8.2nF
4 5
C19 1F
6 7 8
D10 1A, 20V L1: L2: T1: T2: Premier Magnetics #TSD-734 33H, 10A DC Premier Magnetics #TSD-736 Premier Magnetics #TSD-735
ML4824
C18 470pF
R6 41.2k
R10 6.2k
C17 220pF
Premier Magnetics: (714) 362-4211
C11 10nF
Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33.
12
REV. 1.0.4 6/6/01
PRODUCT SPECIFICATION
ML4824
Mechanical Dimensions inches (millimeters)
Package: P16 16-Pin PDIP
0.740 - 0.760 (18.79 - 19.31) 16
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.02 MIN (0.50 MIN) (4 PLACES)
1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
REV. 1.0.4 6/6/01
13
ML4824
PRODUCT SPECIFICATION
Mechanical Dimensions inches (millimeters)
Package: S16W 16-Pin Wide SOIC
0.400 - 0.414 (10.16 - 10.52) 16
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE 0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
14
REV. 1.0.4 6/6/01
ML4824
PRODUCT SPECIFICATION
Ordering Information
Part Number ML4824CP-1 ML4824CP-2 ML4824CS-1 ML4824CS-2 ML4824IP-1 ML4824IP-2 ML4824IS-1 ML4824IS-2 PWM Frequency 1 x PFC 2 x PFC 1 x PFC 2 x PFC 1 x PFC 2 x PFC 1 x PFC 2 x PFC Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C -40C to 85C Package 16-Pin PDIP (P16) 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W) 16-Pin Wide SOIC (S16W) 16-Pin PDIP (P16) 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W) 16-Pin Wide SOIC (S16W)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com
6/6/01 0.0m 003 Stock#DS30004824 (c) 2001 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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